Dmitry Ponomarev Conferences

  • "SCRAP: Architecture for Signature-Based Protection From Code Reuse Attacks" Mehmet Kayaalp, Junaid Nomani, Timothy Schmitt, Dmitry Ponomarev, Nael Abu-Ghazaleh to appear in the 19th International Symposium on High Performance Computer Architecture (HPCA),Shenzhen, China, February 2012.
  • "Branch Regulation: Low Overhead Protection From Code Reuse Attacks" Mehmet Kayaalp, Meltem Ozsoy, Nael Abu-Ghazaleh, Dmitry Ponomarev 39th International Symposium on Computer Architecture (ISCA),Portland, OR, June 2012.
  • "Characterizing and Understanding PDES Behavior on Tilera Architecture" Deepak Jagtap, Ketan Bahulkar, Dmitry Ponomarev and Nael Abu-Ghazaleh 26th ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS),Zhangjiajie, China, July 2012.
  • "Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation" Ketan Bahulkar, Jingjing Wang, Nael Abu-Ghazaleh and Dmitry Ponomarev 26th ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS),Zhangjiajie, China, July 2012.
  • "Performance Analysis of a Multithreaded PDES Simulator on Multicore Clusters" Jingjing Wang, Dmitry Ponomarev and Nael Abu-Ghazaleh 26th ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS),Zhangjiajie, China, July 2012 (short paper).
  • "Optimization of Parallel Discrete Event Simulator for Multi-core Systems" Deepak Jagtap, Nael Abu-Ghazaleh and Dmitry Ponomarev 26th International Parallel and Distributed Processing Symposium (IPDPS), Shanghai, China, May 2012.
  • "CacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors" Dmitry Evtyushkin, Peter Panfilov, Dmitry Ponomarev 11th International Conference on Parallel Computing Technologies (PaCT), Kazan, Russia, September 2011.
  • "TPM-SIM: A Framework for Performance Evaluation of Trusted Platform Modules" Jared Schmitz, Jason Loew, Jesse Elwell, Dmitry Ponomarev, Nael Abu-Ghazaleh 48th Design Automation Conference (DAC'11), San Diego, June 2011.
  • "SIFT: A Low-Overhead Dynamic Information Flow Tracking Architecture for SMT Processors" Meltem Ozsoy, Dmitry Ponomarev, Nael Abu-Ghazaleh, Tameesh Suri 8th ACM International Conference on Computing Frontiers (CF'11), Ischia, Italy, May 2011.
  • "A Co-Processor Approach for Accelerating Data-Structure Intensive Algorithms" Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick Madden,IEEE International Conference on Computer Design (ICCD), Amsterdam, October 2010.
  • "Performance Evaluation of PDES on Multicore Clusters" Ketan Bahulkar, Nicole Hofmann, Deepak Jagtap, Nael Abu-Ghazaleh, Dmitry Ponomarev,14th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications (DS-RT), Fairfax, VA, October 2010.
  • "A Predictive Model For Cache-based Side Channels in Multicore and Multithreaded Microprocessors" Leonid Domnitser, Nael Abu-Ghazaleh, Dmitry Ponomarev,Fifth International Conference "Mathematical Methods, Models and Architectures for Computer Network Security", Saint-Petersburg, Russia, September 2010.
  • "Customized Architectures for Faster Route Finding in GPS-Based Navigation Systems" Jason Loew, Dmitry Ponomarev, Patrick Madden,IEEE Symposium on Application Specific Processors (SASP), June 2010.
  • "A Two-tiered Modelling Framework for Undergraduate Computer Architecture Courses" Jason Loew and Dmitry Ponomarev,Workshop on Computer Architecture Education, held in conjunction with MICRO-42.
  • "MPTLsim: A Simulator for x86 Multicore Processors" Hui Zeng, Matt Yourst, Kanad Ghose and Dmitry Ponomarev,46th Design Automation Conference (DAC-2009), San Fransisco, July 2009.
  • "Energy Efficient Renaming with Register Versioning" Hui Zeng, Ju-Young Jung, Kanad Ghose and Dmitry Ponomarev,International Symposium on Low Power Electronics and Design (ISLPED-2009), San Fransisco, August 2009.
  • "Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures" Hui Zeng, Kanad Ghose and Dmitry Ponomarev, 38th International Conference on Parallel Processing (ICPP-2009), Vienna, September 2009.
  • "Hiding Communication Delays in Clustered Microarchitectures" Robert LaDuca, Joseph Sharkey and Dmitry Ponomarev, 20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.
  • "Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures" Balaji Vijayan and Dmitry Ponomarev,20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo
  • Grande, Brasil, October 2008.
  • "Aggressive Scheduling and Speculation in Multithreaded Architectures: Is It Worth Its Salt?" Jason Loew and Dmitry Ponomarev,20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.
  • "Two-Level Reorder Buffers: Accelerating Memory-bound Applications on SMT Architectures" Jason Loew and Dmitry Ponomarev,37th International Conference on Parallel Processing (ICPP), September 2008.
  • "An L2-Miss-Driven Early Register Deallocation for SMT Processors" Joseph Sharkey, Dmitry Ponomarev,21st ACM International Conference on Supercomputing (ICS'07),Seattle, WA, June 2007.
  • "Trade-offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors" Joseph Sharkey, Nayef Abu-Ghazaleh, Dmitry Ponomarev, Kanad Ghose and Aneesh Aggarwal, 13th IEEE International Conference on High-Performance Computing (HiPC'06),Bangalore, India, December 2006, pp.135-147.
  • "Adaptive Reorder Buffers for SMT Processors" Joseph Sharkey, Deniz Balkan, Dmitry Ponomarev,15th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT'06),Seattle, WA, September 2006, pp.244-253.
  • "SPARTAN: Speculative Avoidance of Register Allocations to Transient Values for Performance and Energy-Efficiency" Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose,15th IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT'06),Seattle, WA, September 2006, pp.265-274.
  • "Selective Writeback: Exploiting Transient Values for Performance and Energy-Efficiency" Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose,IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'06),Tegernsee, Germany, October 2006.
  • "Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch" Joseph Sharkey and Dmitry Ponomarev,35th International Conference on Parallel Processing (ICPP'06),Columbus OH, August 2006, pp.329-336.
  • "Address-Value Decoupling for Early Register Deallocation" Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev and Aneesh Aggarwal,35th International Conference on Parallel Processing (ICPP'06),Columbus OH, August 2006, pp.337-343.
  • "Exploiting Short-Lived Values for Low-Overhead Transient Fault Recovery" Nayef Abu-Ghazaleh, Joseph Sharkey, Dmitry Ponomarev and Kanad Ghose, appear in Workshop on Architectural Support for Gigascale Integration (ASGI'06), held in conjunction with ISCA-33, Boston, MA, June 2006.
  • "Efficient Instruction Schedulers for SMT Processors" Joseph Sharkey and Dmitry Ponomarev, 12th International Symposium on High Performance Computer Architecture (HPCA-12), Austin TX, February 2006, pp.303-313.
  • "Scalable, Low-Complexity Instruction Schedulers for SMT Processors" Joseph Sharkey, Deniz Balkan, Dmitry Ponomarev,2nd IBM Watson Conference on the Interaction between Architecture, Circuits and Compilers (P=ac2), October 2005.
  • "Power-Efficient Wakeup Tag Broadcast" Joseph Sharkey, Kanad Ghose, Dmitry Ponomarev, Oguz Ergin,23rd IEEE International Conference on Computer Design (ICCD'05), San Jose, CA, October 2005.
  • "Non-Uniform Instruction Scheduling" Joseph Sharkey, Dmitry Ponomarev,11th International ACM/IEEE Euro-Par Conference, Lisbon, Portugal, August-September 2005. Acceptance rate - 31%.
  • "Instruction Recirculation: Eliminating Counting Logic in Wakeup Free Schedulers" Joseph Sharkey, Dmitry Ponomarev,11th International ACM/IEEE Euro-Par Conference, Lisbon, Portugal, August-September 2005. Acceptance rate - 31%
  • "Instruction Packing: Reducing Power and Delay of the Dynamic Scheduling Logic" Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin,IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'05), San Diego, CA, August 2005.Acceptance rate for full papers - 9%
  • "Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure" Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev, 37th IEEE/ACM International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004.
  • "Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization" Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin, 4th Workshop on Power-Aware Computer Systems (PACS), held in conjuncton with the 37th IEEE/ACM International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004.
  • "Selective Writeback: Improving Processor Performance and Energy-Efficiency" Deniz Balkan, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose, 1st Watson Conference on Interaction between Architecture, Circuits and Compilers (P=ac2 conference),IBM Research Center at Yorktown Heights, October 2004, pp.171-180.
  • "Predicting, Detecting and Exploiting Transient Values" Deniz Balkan, Dmitry Ponomarev, Kanad Ghose, 2nd Value Prediction and Value-based Optimization Workshop, in conjunction with ASPLOS-XI, October 2004, pp.18-25.
  • "Increasing Processor Performance Through Early Register Release" Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose, 22nd IEEE International Conference on Computer Design (ICCD'04), October 2004, pp.480-487.
  • "Distributed Reorder Buffer Schemes for Low Power" Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose,21st IEEE International Conference on Computer Design] (ICCD'03), San Jose, CA, October 2003, pp.364-370.
  • "Reducing Datapath Energy Through the Isolation of Short-Lived Operands" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose,12th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'03), New Orleans, September 2003, pp.258-268.
  • "Reducing Reorder Buffer Complexity Through Selective Operand Caching" Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose,IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED'03), Seoul, South Korea, August 2003, pp. 235-240.
  • "Power Efficient Comparators for Long Arguments in Superscalar Processors" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose,IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED'03), Seoul, South Korea, August 2003, pp. 378-383.
  • "A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors" Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev, 20th IEEE International Conference on Computer Design (ICCD'02), Freiburg, Germany, September 2002, pp.118-121.
  • "AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors" Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose,5th Design, Automation and Test in Europe Conference (DATE'02), Paris, France, March 2002, pp. 124-129.
  • "Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources" Dmitry Ponomarev, Gurhan Kucuk and Kanad Ghose,34th IEEE/ACM International Symposium on Microarchitecture (MICRO-34),December 2001, pp. 90-101.
  • "Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors" Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter Kogge, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED'01),Huntington Beach, USA, August 2001, pp. 237-242.
  • "Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters" Dmitry Ponomarev, Kanad Ghose, Eugeny Saksonov,7th ACM Euro-Par Conference, Manchester, UK. Published as LNCS 2150, Springer-Verlag, August 2001, pp.86-95.
  • "Dynamic Allocation of Datapath Resources for Low Power" Dmitry Ponomarev, Gurhan Kucuk and Kanad Ghose,Workshop on Complexity-Effective Design (WCED'01), 28th International Symposium on Computer Architecture (ISCA-28),Goteborg, Sweden, June 2001.
  • "Power Reduction in Superscalar Datapaths Through Dynamic Bit-Slice Activation" Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose,International Workshop "Innovative Architecture for Future Generation High-Performance Processors and Systems" (IWIA'01),January 2001, pp.16-24. Invited paper.
  • "Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors" Kanad Ghose, Dmitry Ponomarev, Gurhan Kucuk, Andrew Flinders, Peter M.Kogge, Nikzad Toomarian,Kool Chips Workshop, 33rd International Symposium on Microarchitecture ( MICRO-33),Monterey, CA, December 2000.
  • A Comparative Study of Some Network Subsystem Organizations" Dmitry Ponomarev and Kanad Ghose,5th IEEE/ACM International Conference on High Performance Computing (HiPC 98),Chennai, India, December 1998, pp. 436-443.
  • "Bounded Error Estimate Model of System States Computations for General Service Order Polling Scheme" Eugeny Saksonov and Dmitry Ponomarev,Proceedings of the Int'l. Conf. on Information Systems Analysis and Synthesis, (ISAS'96),July 1996, pp.791-796.
  • Dmitry Ponomarev Journals

  • "Efficiently Securing Systems from Code Reuse Attacks" Mehmet Kayaalp, Meltem Ozsoy, Nael Abu-Ghazaleh, Dmitry Ponomarev Accepted to the IEEE Transactions on Computers.
  • "SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors" Meltem Ozsoy, Dmitry Ponomarev, Nael Abu-Ghazaleh, Tameesh Suri Accepted to the IEEE Transactions on Computers.
  • "Non-Monopolizable Caches: Low-Complexity Mitigation of Cache Side-Channel Attacks." Leonid Domnitser, Aamer Jaleel, Jason Loew, Nael Abu-Ghazaleh and Dmitry Ponomarev Transactions on Architecture and Code Optimization (TACO), Special Issue of High Performance and Embedded Architectures and Compilers. Also to be presented at HIPEAC 2012 conference, Paris, France, January 2012.
  • "Reducing Register Pressure in SMT Processors through L2-Miss-Driven Early Register Release" Joseph Sharkey, Jason Loew, Dmitry Ponomarev,ACM Transactions on Architecture and Code Optimization (ACM TACO), Vol. 5, Issue 3, November 2008 .
  • "Predicting and Exploiting Transient Values for Reduced Register File Pressure and Energy Consumption" Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose,IEEE Transactions on Computers, Vol.57, No 1, January 2008, pp.82-95.
  • "Selective Writeback: Reducing Register File Pressure and Energy Consumption" Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No 6, June 2008, pp.650-661.
  • "Exploiting Operand Availability for Efficient Simultaneous Multithreading" Joseph Sharkey, Dmitry Ponomarev,IEEE Transactions on Computers, Vol. 55, No 2., February 2007, pp.208-223.
  • "Instruction Packing: Toward Fast and Energy-Efficient Instruction Scheduling" Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin,ACM Transactions on Architecture and Code Optimization (ACM TACO), vol.3, No 2, June 2006, pp.156-181.
  • "Early Register Deallocation Mechanisms Using Checkpointed Register Files" Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose,IEEE Transactions on Computers, vol.55, No 9, pp.1153-1166, September 2006.
  • "Dynamic Resizing of Superscalar Datapath Components for Energy-Efficiency" Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose,IEEE Transactions on Computers, Volume 55, No.2, February 2006, pp.199-213.
  • "Reducing the Power Dissipation of Register Alias Tables in High Performance Processors" Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose,IEE Proceedings, Computer and Digital Techniques,Volume 152, Issue 6, November 2005, pp.739-746.
  • "Energy-Efficient Comparators for Superscalar Datapaths" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose,IEEE Transactions on Computers, vol.53, No. 7, July 2004, pp.892-904.
  • "Isolating Short-Lived Operands for Energy Reduction" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose,IEEE Transactions on Computers, vol. 53, No. 6, June 2004, pp.697-709.
  • "Complexity-Effective Reorder Buffer Designs for Superscalar Processors" Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose, IEEE Transactions on Computers, vol.53, No. 6, June 2004, pp.653-665.
  • "Energy-Efficient Issue Queue Design" Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter Kogge,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No 5, October 2003, pp. 789-800.
  • "Energy Efficient Register Renaming" Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose,13th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'03),Torino, Italy, September 2003. Published as Lecture Notes in Computer Science (LNCS 2799), pp.219-228, Springer-Verlag.
  • "Energy-Efficient Design of the Reorder Buffer" Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose,12th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'02) Seville, Spain, September 2002. Published as Lecture Notes in Computer Science, vol. 2451, pp.289-299, Springer-Verlag.
  • Order Dependency in a Single Server Cyclic M/G/1 Multiqueue System Performance" Eugeny Saksonov, Dmitry Ponomarev and Sam Sengupta, Advances in Systems Studies, published by the International Institutefor Advanced Studies in Systems Research and Cybernetics,Baden-Baden,Germany, August 1995, pp.54-58.
  • "Estimation of Systems States in a Single Server M/G/1 Multiqueue System in a Cyclic Access Scheme" Eugeny Saksonov, Dmitry Ponomarev and Sam Sengupta, Advances in Computer Cybernetics, vol.III, published by the International Institute for Advanced Studies in Syst. Research and Cybernetics,Baden-Baden, Germany, August 1995, pp.49-53.
  • "Exact Joint Queue Length Distribution for the Exhaustive Polling" Eugeny Saksonov and Dmitry Ponomarev, Advances in Artificial Intelligence and Engineering Cybernetics, Vol.III, published by the International Institute for Advanced Studies in Systems Research and Cybernetics, Baden-Baden, Aug. 1996, pp.149-153.